Advances in semiconductor manufacturing technology have led to the integration of billions of circuit elements, such as transistors, on a single integrated circuit (IC). In order to integrate increasing numbers of circuit elements onto an integrated circuit it has been necessary to reduce the dimensions of the electronic devices (e.g., a metal-oxide-semiconductor (MOS) transistor).
A transistor 10, made using conventional techniques, is shown in FIG. 1 of the accompanying drawings. The transistor 10 includes a substrate 12, a channel region 14, source region 16, drain region 18, source contact 20, drain contact 22, gate dielectric layer 24, gate electrode 26 and spacers 27. The transistor may also include contact terminals 28 and 30 and gate terminal 32.
The gate dielectric layer 24 is formed on the substrate 10, over the channel region 14. The gate electrode 26 is formed on the gate dielectric layer 24. The source and drain regions 16, 18 are formed on opposing sides of the channel region 14 in the substrate. The source and drain contacts 20, 22 are formed over the source and drain regions 16, 18, respectively. The spacers are provided on opposite sides of the gate dielectric layer 24 and gate electrode 26, and over the source and drain regions 16, 18. The gate electrode 26 may be a p-type, n-type or mid-gap metal. The contact terminals 28 and 30 are connected to the source and drain contacts 20 and 22, respectively, and gate terminal 32 is connected to gate electrode 26. As shown in FIGS. 1 and 2, the contacts 20, 22 are separated by a distance from the gate electrode 26. This distance is typically referred to as a registration window.
In use, a voltage is applied to the source region 16 of the transistor 10, causing current to flow through the channel region 14 to the drain 18. A voltage is also applied to the gate electrode 26 of the transistor, which interferes with the current flowing in the channel region 14 of the transistor. The voltage connected to the gate electrode 26 switches the current on and off in the channel region 14 of the transistor at any given time. A circuit diagram of an n-channel transistor is shown in FIG. 3. A circuit diagram of a p-channel transistor is shown in FIG. 4.
If the metallic gate electrode 26 and metallic contacts 20, 22 come into contact, a short circuit occurs. In conventional processes, the registration window and critical dimensions are controlled to ensure that the contacts 20, 22 avoid the gate electrode 26. However, protecting the gate from the contact is becoming more challenging as the gate pitch is getting smaller and registration requirements are becoming more difficult to meet with existing processes. For example, a sub-ten nm contact CD (critical dimension) is required to deliver a manfucaturable registration window for these scaled transistors; however, current processes only allow a registration window of about 15 nm. These contact to gate shorts are substantial yield limiters.